1. Field of the Invention
The present invention relates to a semiconductor device having a resistance memory element.
2. Description of Related Art
A semiconductor device having a resistance memory element is described, for example, in “A Novel Resistance Memory with High Scalability and Nanosecond Switching”, K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada, and H. Narisawa, Technical Digest IEDM 2007, pp. 783-786.
Hereinafter, the configuration of a resistance memory cell will be described with reference to the cited reference.
FIG. 1 is a view used to describe the configuration of a resistance memory cell.
As is shown in FIG. 1, one memory cell MC includes one transistor T1 forming a selector resistor and one resistor R1 forming a memory element. In short, one memory cell includes one transistor and one resistor (1T1R).
A resistance layer 13 and an ion source layer 14 are sandwiched between a bottom electrode (fourth metal layer in FIG. 1) 11 and a top electrode 12 and the memory cell MC functions as a memory element depending on whether a conduction path is present in the resistance layer 13. A resistance layer is an insulator, such as SiO2. An ion source layer is a conductive layer containing at least one type of chalcogen element selected from S, Se, and Te and at least one type of metal element selected from Cu, Ag, and Zn. The conduction path is formed so as to contain these metal elements.
The resistor R1 is made low resistance during a write operation and high resistance during an erase operation.
FIG. 2A and FIG. 2B are views showing the potential relation of the resistance memory cell in states where the resistance is made lower (write) and where the resistance is made higher (erase), respectively. FIG. 3A and FIG. 3B are equivalent circuits of the resistance memory cell in states where the resistance is made lower (write) and where the resistance is made higher (erase), respectively. FIG. 4 is a view showing the relation of a write current value and a cell resistance.
As are shown in FIG. 2A and 2B, write and erase operations are switched by changing the current applied polarities. When the resistance memory cell is in a state where the resistance is made lower (write), as is shown in FIG. 2A, 3 V is applied to the top electrode 12 and 0 V is applied to the bottom electrode 11. Accordingly, metal elements ionized within the ion source layer 14 diffuse into the resistance layer 13 and a conduction path is formed, which makes the memory cell low resistance.
When the resistance memory cell is in a state where the resistance is made higher (erase), as is shown in FIG. 2B, 0 V is applied to the top electrode 12 and 1.7 V is applied to the bottom electrode 11. Accordingly, metal elements diffused within the resistance layer 13 return into the ion source layer 14, which makes the memory cell high resistance.
Referring to FIG. 3A and FIG. 3B, directions of a current in states where the resistance is made lower (write) and where the resistance is made higher (erase) are determined by arrows put across the resistors.
Also, as is shown in FIG. 4, resistance of the memory cell varies with a write current value.
The cited reference describes an example where a multi-valued memory is achieved by controlling a write current.